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a31w33128 series preliminary lcd controller - driver preliminary (december, 2000, version 0.1) amic technology, inc. document title lcd controller - driver revision history rev. no. history issue date remark 0.0 initial issue march 13, 2000 preliminary 0.1 error correction: december 7, 2000 pad assignment & boot capacitor connection: c1+ ? c1 - c1 - ? c1 + c2+ ? c2 - c2 - ? c2+
a31w33128 series preliminary lcd controller - driver preliminary (december, 2000, version 0.1) 1 amic technology, inc features n power supply range : 2.4v to 5.5v 2.7v to 11.0v (lcd drive) n internal lcd drivers : 128 segment signal drivers 17 /33 commons signal drivers n power save current (<1ua) n on chip 128 x 65 display data ram n 8 bi t 80/68 - series parallel interface ,serial interface n build - in rc oscillator or external clock input (18khz) n 1:4 / 1:5 / 1:6.7(default) bias ratio n 1:2 to 1:4 bias ratio (external) n 16 level internal contrast control n build - in temperature compensation circui t n on chip internal dc/dc converter / external power supply n dual/ triple booster n 2 internal icon common output systems n tcp package, gold bumps the a31w33128 is a cmos lcd driver, which has 128 segment, and 17 or 33 common graphic display . it has 80/68 - series 8 bit parallel and serial interface capability for operating with general cpu. the internal 65 x 128 display data ram makes the display of both graphics and characters possible. besides the general lcd driver features, it has on chip lcd bias divider circuit such that minimize external component required in system application.
a31 w33128 series preliminary (december, 2000, version 0.1) 2 amic technology, inc block diagram 1. block overview page address register start line register & counter oscillating circuit lcd timing circuit power on reset display ram 8320 bits page address decode start line address decoder data latch column address decoder line control start line register lcd driver data input/ output column address register & counter display data control mpu interface for 68-series & 80-series c1- command decoder a0 p/s c68/80 cs r/w e lcd power supply circuit status register c1+ c2- c2+ v out v cnt fnc1 fnc2 v 1 to v 5 vdd d0 to d7 vss comicn1,2 com1 to 32 seg1 to 128 osc1 osc2
a31 w33128 series preliminary (december, 2000, version 0.1) 3 amic technology, inc block diagram 2. lcd power supply circuit block diagram triple booster & double booster reference voltage voltage regular reference regular adjustment circuit bias resister voltage follower command register v4 v3 v2 v1 v5 v out v cnt c1- c1+ c2- c2+ clk fcn1 fcn2
a31 w33128 series preliminary (december, 2000, version 0.1) 4 amic technology, inc pad assignment test0 test1 test2 test3 test4 test5 nc vdd vdd vdd cs a0 r/w e p/s c68/80 osco osci vss vss vss vss nc d0 d1 nc d2 d3 nc d4 d5 nc d6 d7 nc fnc2 fnc1 vss vss vss test6 nc v out c2+ c2- nc c1+ c1- nc v cnt test7 test8 vdd test9 v5 v4 v3 v2 v1 icn1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 icn2 17 19 21 23 25 27 29 31 18 20 22 26 24 28 30 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . com output seg128 seg127 seg126 seg125 seg5 seg4 seg3 seg2 seg1 com output (0,0) control pins . pad pitch segment driver 65um comon driver 65um control pad 120um . gold bump size drive 43x85um input pin 72x85um . gold bump height 18um (typ.) vdd vss vdd vdd vdd chip identification marks (the identification marks are larger than the actual scaling) 50 50 50 50 50 50 50 50 (4096.5, 740) (-4097.5, 740) (the identification marks are made of ai patterns) unit : um
a31 w33128 series preliminary (december, 2000, version 0.1) 5 amic technology, inc pad coordinates unit: m m (the o rigin is the center of the chip) no. pin name x y no. pin name x y 1 test0 - 3877.5 - 897.5 64 test9 3877.7 - 897.5 2 test1 - 3807.5 - 897.5 65 nc 4103.5 - 717.5 3 test2 - 3737.5 - 897.5 66 com17 4103.5 - 647.5 4 test3 - 3667.5 - 897.5 67 com18 4103.5 - 577.5 5 test4 - 3597.5 - 897.5 68 com19 4103.5 - 507.5 6 test5 - 3527.5 - 897.5 69 com20 4103.5 - 437.5 7 nc - 3457.5 - 897.5 70 com21 4103.5 - 367.5 8 vdd - 3371.5 - 897.5 71 com22 4103.5 - 297.5 9 vdd - 3251.5 - 897.5 72 com23 4103.5 - 227.5 10 vdd - 3131.5 - 897.5 73 com24 4103.5 - 157.5 11 vdd - 3011.5 - 897.5 74 com25 4103.5 - 87.5 12 cs - 2891.4 - 897.5 75 com26 4103.5 - 17.5 13 a0 - 2763.6 - 897.5 76 com27 4103.5 52.5 14 r/w - 2635.8 - 897.5 77 com28 4103.5 122.5 15 e - 2508 - 897.5 78 com29 4103.5 192.5 16 p/s - 2380.2 - 897.5 79 com30 4103.5 262.5 17 c68/80 - 2252.4 - 897.5 80 com31 4103.5 332.5 18 osco - 2124.6 - 897.5 81 com32 4103.5 402.5 19 osci - 1996.8 - 897.5 82 comicn2 4103.5 472.5 20 vss - 1876.8 - 897.5 83 nc 4103.5 548.5 21 vss - 1756.8 - 897.5 84 seg1 4127.5 897.5 22 vss - 1636.8 - 897.5 85 seg2 4062.5 897.5 23 vss - 1516.8 - 897.5 86 seg3 3997.5 897.5 24 nc - 1430.8 - 897.5 87 seg4 3932.5 897.5 25 d0 - 1264.2 - 897.5 88 seg5 3867.5 897.5 26 d1 - 999.8 - 897.5 89 seg6 3802.5 897.5 27 nc - 835.2 - 897.5 90 seg7 3737.5 897.5 28 d2 - 670.6 - 897.5 91 seg8 3672.5 897.5 29 d3 - 406.2 - 897.5 92 seg9 3607.5 897.5 30 nc - 241.6 - 897.5 93 seg10 3542.5 897.5 31 d4 - 77 - 897.5 94 seg11 3477.5 897.5 32 d5 187.4 - 897.5 95 seg12 3412.5 897. 5 33 nc 352 - 897.5 96 seg13 3347.5 897.5 34 d6 516.6 - 897.5 97 seg14 3282.5 897.5 35 d7 781 - 897.5 98 seg15 3217.5 897.5 36 nc 945.6 - 897.5 99 seg16 3152.5 897.5 37 fnc2 1049.2 - 897.5 100 seg17 3087.5 897.5 38 fnc1 1177 - 897.5 101 seg18 3022.5 897.5 39 vss 1298.7 - 897.5 102 seg19 2957.5 897.5 40 vss 1418.7 - 897.5 103 seg20 2892.5 897.5 41 vss 1538.7 - 897.5 104 seg21 2827.5 897.5 42 vss 1658.7 - 897.5 105 seg22 2762.5 897.5 43 test6 1744.7 - 897.5 106 seg23 2697.5 897.5 44 nc 1814.7 - 897 .5 107 seg24 2632.5 897.5 45 v out 1900.7 - 897.5 108 seg25 2567.5 897.5 46 nc 1981.7 - 897.5 109 seg26 2502.5 897.5 47 c2+ 2062.7 - 897.5 110 seg27 2437.5 897.5 48 c2 - 2182.7 - 897.5 111 seg28 2372.5 897.5 49 c1+ 2302.7 - 897.5 112 seg29 2307.5 897.5 50 c1 - 2422.7 - 897.5 113 seg30 2242.5 897.5 51 nc 2503.7 - 897.5 114 seg31 2177.5 897.5 52 v cnt 2589.7 - 897.5 115 seg32 2112.5 897.5 53 test7 2675.7 - 897.5 116 seg33 2047.5 897.5 54 test8 2745.7 - 897.5 117 seg34 1982.5 897.5 55 vdd 2831.7 - 897.5 118 seg35 1917.5 897.5 56 vdd 2951.7 - 897.5 119 seg36 1852.5 897.5 57 vdd 3071.7 - 897.5 120 seg37 1787.5 897.5 58 vdd 3191.7 - 897.5 121 seg38 1722.5 897.5 59 v1 3311.7 - 897.5 122 seg39 1657.5 897.5 60 v2 3431.7 - 897.5 123 seg40 1592.5 897.5 61 v3 3551.7 - 897.5 124 seg41 1527.5 897.5 62 v4 3671.7 - 897.5 125 seg42 1462.5 897.5 63 v5 3791.7 - 897.5 126 seg43 1397.5 897.5
a31 w33128 series preliminary (december, 2000, version 0.1) 6 amic technology, inc pad coordinates (continued) unit: m m (the origin is the center of the chip) no. pin name x y no. pin name x y 127 seg 44 1332.5 897.5 190 seg107 - 2762.5 897.5 128 seg45 1267.5 897.5 191 seg108 - 2827.5 897.5 129 seg46 1202.5 897.5 192 seg109 - 2892.5 897.5 130 seg47 1137.5 897.5 193 seg110 - 2957.5 897.5 131 seg48 1072.5 897.5 194 seg111 - 3022.5 897.5 132 seg49 100 7.5 897.5 195 seg112 - 3087.5 897.5 133 seg50 942.5 897.5 196 seg113 - 3152.5 897.5 134 seg51 877.5 897.5 197 seg114 - 3217.5 897.5 135 seg52 812.5 897.5 198 seg115 - 3282.5 897.5 136 seg53 747.5 897.5 199 seg116 - 3347.5 897.5 137 seg54 682.5 897.5 200 seg117 - 3412.5 897.5 138 seg55 617.5 897.5 201 seg118 - 3477.5 897.5 139 seg56 552.5 897.5 202 seg119 - 3542.5 897.5 140 seg57 487.5 897.5 203 seg120 - 3607.5 897.5 141 seg58 422.5 897.5 204 seg121 - 3672.5 897.5 142 seg59 357.5 897.5 205 seg122 - 3737.5 897.5 143 seg60 292.5 897.5 206 seg123 - 3802.5 897.5 144 seg61 227.5 897.5 207 seg124 - 3867.5 897.5 145 seg62 162.5 897.5 208 seg125 - 3932.5 897.5 146 seg63 97.5 897.5 209 seg126 - 3997.5 897.5 147 seg64 32.5 897.5 210 seg127 - 4062.5 897.5 148 seg65 - 32.5 897.5 211 seg128 - 4127.5 897.5 149 seg66 - 97.5 897.5 212 nc - 4103.5 542.5 150 seg67 - 162.5 897.5 213 com16 - 4103.5 472.5 151 seg68 - 227.5 897.5 214 com15 - 4103.5 402.5 152 seg69 - 292.5 897.5 215 com14 - 4103.5 332.5 153 seg70 - 35 7.5 897.5 216 com13 - 4103.5 262.5 154 seg71 - 422.5 897.5 217 com12 - 4103.5 192.5 155 seg72 - 487.5 897.5 218 com11 - 4103.5 122.5 156 seg73 - 552.5 897.5 219 com10 - 4103.5 52.5 157 seg74 - 617.5 897.5 220 com9 - 4103.5 - 17.5 158 seg75 - 682.5 897.5 22 1 com8 - 4103.5 - 87.5 159 seg76 - 747.5 897.5 222 com7 - 4103.5 - 157.5 160 seg77 - 812.5 897.5 223 com6 - 4103.5 - 227.5 161 seg78 - 877.5 897.5 224 com5 - 4103.5 - 297.5 162 seg79 - 942.5 897.5 225 com4 - 4103.5 - 367.5 163 seg80 - 1007.5 897.5 226 com3 - 410 3.5 - 437.5 164 seg81 - 1072.5 897.5 227 com2 - 4103.5 - 507.5 165 seg82 - 1137.5 897.5 228 com1 - 4103.5 - 577.5 166 seg83 - 1202.5 897.5 229 comicn1 - 4103.5 - 647.5 167 seg84 - 1267.5 897.5 230 nc - 4103.5 - 717.5 168 seg85 - 1332.5 897.5 169 seg86 - 13 97.5 897.5 170 seg87 - 1462.5 897.5 171 seg88 - 1527.5 897.5 172 seg89 - 1592.5 897.5 173 seg90 - 1657.5 897.5 174 seg91 - 1722.5 897.5 175 seg92 - 1787.5 897.5 176 seg93 - 1852.5 897.5 177 seg94 - 1917.5 897.5 178 seg95 - 1982.5 897.5 179 seg96 - 2047.5 897.5 180 seg97 - 2112.5 897.5 181 seg98 - 2177.5 897.5 182 seg99 - 2242.5 897.5 183 seg100 - 2307.5 897.5 184 seg101 - 2372.5 897.5 185 seg102 - 2437.5 897.5 186 seg103 - 2502.5 897.5 187 seg104 - 2567.5 897.5 188 seg105 - 2632.5 897.5 189 seg106 - 2697.5 897.5
a31 w33128 series preliminary (december, 2000, version 0.1) 7 amic technology, inc input/output pin function pin no. symbol type description 20 - 23, 39 - 42 vss supply ground 8 - 11, 55 - 58 vdd supply power supply pin 18 osco output oscillator output 19 osci input oscillator input 12 cs input chip select input, low active 13 a0 input a0=low: command input. a0=high: display data input and outputs 68 - series r/w=high: read, r/w=low : write 14 r/w input 80 - series : write enable, active low 68 - series : enable clock signal input, active high 15 e input 80 - series : read enable, active low 16 p/s input parallel/serial interface select input high : 8 - bit parallel interface low : serial int erface 17 c68/80 input microprocessor interface select input high : 68 - series interface is selected low : 80 - series interface is selected 25 - 26, 28 - 29, 31 - 32, 34 - 35 d0 - 7 input/ output 8bit bi - directional data bus to be connected to microprocess or?s data bus p/s=high : 8 - bit configuration data bus connection p/s=low : serial interface connection d0 serial data input d1 serial clock input d2 serial data output 84 - 211 seg1 - seg128 output provide the lcd segment driving signal 66 - 81 213 - 228 com1 - com32 output provide the lcd common driving signal 229 82 comicn1 comcn2 output provide the icon common driving signal comicn1 and comicn2 output the same phase waveform. 37 fnc2 input lcd power control input pin 38 fnc1 input lcd power control input pin 42 v out output boosting voltage output 47 c2 + input 2nd - step boosting capacitor negative connection 48 c2 - input 2nd - step boosting capacitor positive connection 49 c1+ input 1 st - step boosting capacitor negative connection 50 c1 - input 1 st - step boosting capacitor positive connection 52 v cnt input lcd power supply voltage control
a31 w33128 series preliminary (december, 2000, version 0.1) 8 amic technology, inc input/output pin function (continued) pin no. symbol type description 59 v1 input 60 v2 input 61 v3 input 62 v4 input 63 v5 input lcd driver bias voltage. they can be supplied externally or generated by the intern al bias divider. 1: 4 bias 1: 5 bias 1: 6.75 bias v1 1/4 x v5 1/5 x v5 1/6.75 x v5 v2 2/4 x v5 2/5 x v5 2/6.75 x v5 v3 2/4 x v5 3/5 x v5 4.75/6.75 x v5 v4 3/4 x v5 4/5 x v5 5.75/6.75 x v5 ? inputs lcd drive bias voltage when using an external lcd power supply circuit. v5 3 v4, v3, v2, v1 > vss 1 - 7, 24, 27, 30, 33, 36, 43 - 44, 46, 51, 53 - 54, 64 - 65, 83, 212, 230 nc open no connection 1 test0 2 test1 3 test2 4 test3 5 test4 6 test5 43 test6 53 test7 54 test8 64 test9 open cannot be wired to the outside
a31 w33128 series preliminary (december, 2000, version 0.1) 9 amic technology, inc commands table bit pattern command a0 e r/w d7 d6 d5 d4 d3 d2 d1 d0 comment set display on/off 0 1 0 1 0 1 0 1 1 1 0 1 d0:0 display off: display goes out, regardless of the cont ent of the display data ram d0:1 display on: normal display set display start line 0 1 0 0 1 display start line address sets the line address of the display data ram output to com1 page address set 0 1 0 1 0 1 1 page address sets the page address of the display data ram. page 8 is assigned to the icon display upper 3 bits of column address set 0 1 0 0 0 0 1 0 upper 3 bits of column address sets upper 3 bits of the display data ram column address lower 4 bits of the column address set 0 1 0 0 0 0 0 lower 4 bits of the column address lower 4 bits of display data ram column address status read 0 0 1 status status read display data write 1 1 0 write data in display data ram writes data of d0 to d7 in the display data ram display data read 1 0 1 read data from display data ram reads data from d0 to d7 from the display data ram adc select 0 1 0 1 0 1 0 0 0 0 0 1 reverses upper or lower display data ram column address d0:0 normal: column addresses 00 to 7fh correspond to segment outputs 1 to 128 d0:1 revers e: column addresses 00 to 7fh correspond to segment outputs 128 to 1 display normal/reverse 0 1 0 1 0 1 0 0 1 1 0 1 d0:0 normal : ?1? makes the display be lit d0:1 reverse : ?0? makes the display be lit the icon display is not reversed display all - l it on/off 0 1 0 1 0 1 0 0 1 0 0 1 d0:0 normal display d0:1 display all - lit duty selection/ alternate common output 0 1 0 1 0 1 0 1 0 * 0 1 0 1 1 d0:0 1/17 duty d0:1 1/33 duty d1:0 common output order: in a numerical order d1:1 common output order: al ternate output to right and left of the chip. read modify write 0 1 0 1 1 1 0 0 0 0 0 increments display data ram column address only during writing end 0 1 0 1 1 1 0 1 1 1 0 read modify write release. reset 0 1 0 1 1 1 0 0 0 1 0 it does not affect the contents of the display data ram. after resetting, display starts according to the reset value: 1.resets the display start line register to the 1st line. 2.resets the column address counter to address 0. 3. resets the page address counter to page 0. 4.clea rs the serial interface counter. 5.turns off the read modify write.
a31 w33128 series preliminary (december, 2000, version 0.1) 10 amic technology, inc commands table (continued) bit pattern command a0 e r/w d7 d6 d5 d4 d3 d2 d1 d0 comment bias selection 0 1 0 0 0 1 0 1 0 d1 d0 d1,d0:0, 0 1/6.75 bias selection d1,d0:0, 1 1/5 bias selection d1,d0:1, 0 1/4 bias selection d1,d0:1, 1 don't care lcd voltage command fine adjustment data 0 1 0 1 0 0 0 0 . 1 0 . 1 0 . 1 0 . 1 minimum value (default) maximum value lcd power supply circuit on/off 0 1 0 0 0 1 0 0 1 0 0 1 d0: 0 lcd pow er supply circuit off d0: 1 lcd power supply circuit on the lcd power supply circuit connected to pinsfnc1, fnc2 starts its operation earlier than the lcd power supply circuit on/off command. icon only display 0 1 0 1 1 0 0 0 d2 boosting control data d2: 0 normal display d2: 1 icon only display boosting control data: selects boosting frequency reference voltage temperature coefficient selection 0 1 0 1 1 1 0 0 1 * 0 1 d0:0 - 0.13%/ c d0:1 +0.01%/ c power save display off, display all - lit on
a31 w33128 series preliminary (december, 2000, version 0.1) 11 amic technology, inc operation of lcd display driver 1. powering on setting sequence recommended command setting sequence: (1) set display off : in order to prevent unnecessary characters from being displayed during powering on of the power . the state is changed to the ? power save mode? after turning on the display all - lit on with the display off. (2) set display all - lit off: normal display operation and the oscillation start. (3) set lcd power supply circuit on (4) set bias select ( 5) set reference voltage temperature compensation coefficient (6) end command input (7) set duty select/alternate common output (8) set display normal/reverse : d0 : 0 normal display data "1" makes the display be lit. d0 : 1 reverse display data "0" makes the display be lit. (9) set display start line address: changing the display start line allows for page change on the display screen as well as vertical smooth scroll. (10) common output sequence (11) icon only display (12) display data wri te: after writing the display data, the column address is automatically incremented. to write the display data in succession after setting the 1st column address to be written by the column address setting command, the column address is not needed to be se t each time. the icon display data is valid for only d0. write ?l? or data to be displayed in all display data ram before turning the display on. (13) display on 2. set powering off, power save mode set powering off sequence : (1) set display off (2) set lcd power supply circuit off power save mode : when in power save mode, the command sleeps the system : internal oscillating circuit and lcd power supply circuit are stopped. the segment and common outputs are fixed at vss level. the lcd displ ay goes out. the contents of the display data ram, the command and the address before the power save mode do not change. combination of commands state display on display on display off display off display all - lit off display all - lit o n display all - lit off display all - lit on normal display operation all - lit display aii - off power save
a31 w33128 series preliminary (december, 2000, version 0.1) 12 amic technology, inc 3. mpu interface select the parallel 68 - series, 80 - series interface or serial interface can be selected by p/s, c68/80 pin setup: p/s pin c68/80 pin mpu interface l 80 - series interface selected h h 68 - series interface selected l don't care serial interface selected 3.1 mpu parallel 68 - series and 80 - series interface the parallel interface consists of 8 bi - directional data pins (d0 - d7), r/w( wr ), a0, e( rd ), cs in order to match the operating frequency of display ram with that of the microprocessor, some pipeline processing is internally performed which requires the insertion of a dummy re ad before the first actual display data read. a31w33128 pin name a0 e r/w cs d0 - d7 68 - series mpu signal a0 e r/w cs d0 - d7 80 - series mpu signal a0 rd wr cs d0 - d7 3.2 mpu serial interface the serial interface consists of serial clock input sclk, serial data input sdi and output sdo, chip select cs , p/s, r/w, a0. when the e pin to be open and the serial interface is selected by s etting p/s to ?l?, the instruction code is the same as for the parallel interface .by setting cs to ?l?. the serial interface circuit enters an operating state. and by setting cs to ?h?, it will reset the serial in terface circuit and initialized the counter. data is input in the order of d0, d1, d2,....d7. the displayed data and commands are written at the rising edge of the sclk. but the displayed data and status are read at the falling edge of the sclk. data read needs a dummy read. when in reset condition, the sdo pin will be driven to ?h?, and the status reading will be invalidated. d0 (sdi) : serial data input d1 (sclk) : serial clock input d2 (sdo) : serial data output d3 to d7 : open e : open c68/80 : o pen a0 r/w operation l l command input h h display data read l h status read h l display data write 4. command execution when the input at d0 - d7 is interpreted as a command and it will be decoded and written to the corresponding command register. t he user can input the commands continuously without confirming the busy flag of status command register because the command is completely executed within the cycle time (tcyc) according to the timing characteristics of the command input. but that re - inputt ing the command within the executed cycle time is inhibited.
a31 w33128 series preliminary (december, 2000, version 0.1) 13 amic technology, inc 5. data bus select when cs is held at ?h? level, the d0 - d7 is in high impedance state. 68/80 - series shared 68 - series 80 - series a0 r/w e r/w description 1 1 0 1 reads fr om display data ram 1 0 1 0 writes to display data ram 0 1 0 1 reads status 0 0 1 0 command write to internal register 6. display data ram the display data ram is made of dual port ram. the size of the ram is 64 x 128 + 128 = 8320 bits. write ?l? or dat a to be displayed in all display data ram before turning the display on. 7. accessing the display data ram from mpu in order to match the operating frequency of display data ram with that of the mpu, a dummy read is required before the first actual display d ata read. when the mpu reads the display data ram, the first dummy read cycle stores the first read data in the bus holder, and then at the next read cycle the mpu read the first read data from the bus holder. it does not need a dummy cycle when mpu write s data to the display data ram. when the mpu write data to display data ram, once the data is stored in the bus holder, then it is written to display data ram before the next data write cycle. 8. set column address (higher, lower nibble) this command specifi es the column address (higher and lower nibble) of the display data ram. the column address will be incremented by each data access after it is pre - set by the mpu. 9. set page address(0 - 8) this command positions the page address to 1 of 9 possible positions i n display data ram. page 0 - 7 are the graphic display area, and the page 8 are the icon display area. 10. set display start line (0 - 63) the command is used to change the display page or smooth scroll. with the display start line value equals to 0, d0 of page 0 is mapped to com1. the display start line values of 0 to 63 are assigned to page 0 to 7.
a31 w33128 series preliminary (december, 2000, version 0.1) 14 amic technology, inc 11. status read this command shows the status of a31w33128 busy : d7 =0 : the a31w33128 is not busy 1 : the a31w33128 is in internal operation or reset state. ad c : d6 =0 : adc reverse : column addresses 00 to 7fh correspond to segment outputs 128 to 1. 1 : adc normal : column addresses 00 to 7fh correspond to segment outputs 1 to 128. on/off : d5 =0 : display on 1 : display off reset : d4 =0 : in normal operation state 1 : internal reset operation state psave : d3 =0 : in normal operation state 1 : in power save state icon : d2 =0 : in normal operation state 1 : in icon only display state drev : d1 =0 : display normal 1 : display reverse alon : d0 =0 : normal display 1 : display all - lit on when a serial interface is selected, the status read from the sdo pin is always high level during reset operation. 12. 1/33 ,1/17 duty select, alternate common output common outpu t sequence at duty 1/33 output sequence common driving signal output in numerical common driving signal alternate output 1 com1 com1 2 com2 com17 3 com3 com2 . . . . . . 16 com16 com9 17 com17 com25 . . . . . . 31 com31 com16 32 com32 com32 33 co micn1,2 comicn1,2 common output sequence at duty 1/17 output sequence common driving signal output in numerical 1 com1,17 2 com2,18 3 com3,19 . . . . 15 com15,31 16 com16,32 17 comicn1,2 the common output at duty 1/17 only has in numerical sequence.
a31 w33128 series preliminary (december, 2000, version 0.1) 15 amic technology, inc 13. read modify write , end read modify write this command puts the chip in read modify write mode. in this mode the column address is saved before entering the mode, and is incremented by display data write but not by display data read. during th e read modify write mode, all commands are usable except the column address set command. end this command relieves the a31w33128 from read modify write mode. the column address that is saved before entering read modify write mode will be restored. 14. boostin g frequency select select the boosting frequency: d1 d0 boosting freq. 0 0 fosc/2 0 1 fosc/4 1 0 fosc/8 1 1 fosc/16 15. rc oscillator circuit the built - in rc oscillator generates the clock for the boosting frequency, and is also used in the display timin g. when using the external clock, the external clock is input to osci, and osco is left floating. used built - in rc oscillator , rf = 1 m w 1/17 duty frame freq. 66.17 hz at fosc = 18 khz 1/33 duty frame freq.68.18 hz at fosc = 18 khz 16. reference voltage temperature compensation coefficient select this command is to set one out of 2 different temperature coefficients in order to match various liquid crystal temperature grades. d v ref = 1 2 1 ref 2 ref t t )i (t iv )i (t iv - - t 2 > t 1
a31 w33128 series preliminary (december, 2000, version 0.1) 16 amic technology, inc v5= ra + rb ra x vref (v) rb ra vref vss vcnt v5 + - vdd=3v vss example of booster output double vout = 6v triple vout = 9v 17. lcd power supply circuit the lcd power supply circuit generates the lcd voltage needed for display output, which is controlled by pins fnc1 ,fnc2 and lcd power supply circuit on/off command. it consists of: 1. doubler/tripler dc - dc voltage converter. 2. voltage regulator and lcd voltage co mmand fine adjustment circuit. 3. lcd bias resistor and voltage follower fnc2 fnc1 doubler/tripler circuit voltage regulator circuit lcd bias resistor/ voltage follower circuit l h l h l l h h on off off off on off on off on off on on fnc1 and fnc2 must connect to vdd or vss. don?t connect the external power supply with the built - in lcd power supply circuit on, it may lead to a breakdown. 17.1 doubler/tripler it is the 2x, 3x dc - dc voltage converter. please refer to application notes. 17.2 lcd voltage adjustment there are two methods of adjusting the lcd voltage as follows: 17.2.1 voltage regulator voltage regulator output v5 is adjusted by externally attached ra and rb.
a31 w33128 series preliminary (december, 2000, version 0.1) 17 amic technology, inc 17.2.2 lcd voltage command fine adjustment control software control of 16 v oltage levels adjustment of v5 voltage by set 4 bits of the data bus. it can adjust the lcd contrast. 17.3 lcd bias voltage when use built - in lcd bias resistor, software can control the 1/6.7, 1/5,1/4 bias ratio to match the characteristic of lcd panel. 17.4 voltage follower the voltage follower buffers the lcd bias voltage created by the built - in bias resistor, and supplies it to the lcd drive circuit.
a31 w33128 series preliminary (december, 2000, version 0.1) 18 amic technology, inc interface 1. parallel interface 1.1 display data write ( the 80 - series interface) 1.2 display data read ( the 80 - series interface) n n+1 n+2 n+3 n+3 n+2 n+1 n r/w data bus holder r/w internal busy flag mp internal timing n x n n+1 r/w data bus holder r/w internal busy flag mp internal timing address set address n dummy read data read address n data read address n+1 n n+1 n+2 n+2 n+1 n x e e column address
a31 w33128 series preliminary (december, 2000, version 0.1) 19 amic technology, inc d0 cs r/w d1 d2 d3 d4 d5 d6 d7 d0 d0 d1 d2 d3 d4 d5 d6 d7 d0 a0 d1 (sclk) d0 (sdi) d2 (sdo) 2 serial interface serial interface display data write/read timing a0 r/w d0 (sdi) d2 (sdo) 0 0 command write invalid 0 1 invalid status read 1 0 data write invalid 1 1 invalid data read (note) note: data read needs a dummy read
a31 w33128 series preliminary (december, 2000, version 0.1) 20 amic technology, inc display data ram vs address page address page0 00 h 01 h 02 h 03 h 04 h 05 h 06 h 07 h 0, 0, 0, 0 line address d0 d1 d2 d3 d4 d5 d6 d7 page1 08 h 09 h 0a h 0b h 0c h 0d h 0e h 0f h 0, 0, 0, 1 d0 d1 d2 d3 d4 d5 d6 d7 page2 10 h 11 h 12 h 13 h 14 h 15 h 16 h 17 h 0, 0, 1, 0 d0 d1 d2 d3 d4 d5 d6 d7 page3 18 h 19 h 1a h 1b h 1c h 1d h 1e h 1f h 0, 0, 1, 1 d0 d1 d2 d3 d4 d5 d6 d7 page4 20 h 21 h 22 h 23 h 24 h 25 h 26 h 27 h 0, 1, 0, 0 d0 d1 d2 d3 d4 d5 d6 d7 page5 28 h 29 h 2a h 2b h 2c h 2d h 2e h 2f h 0, 1, 0, 1 d0 d1 d2 d3 d4 d5 d6 d7 page6 30 h 31 h 32 h 33 h 34 h 35 h 36 h 37 h 0, 1, 1, 0 d0 d1 d2 d3 d4 d5 d6 d7 page7 38 h 39 h 3a h 3b h 3c h 3d h 3e h 3f h 0, 1, 1, 1 d0 d1 d2 d3 d4 d5 d6 d7 1, 0, 0, 0 d0 page8 40 h column address adc d0= "0" seg pin adc d0= "1" 00 01 02 03 04 05 06 07 .............. 7f 7e 7d 7c 7b 7a 79 78 .............. 1 2 3 4 5 6 7 8............... .... .... ...... 01 00 ...... 3f 40 7e 7f .... .... ...... 127 128 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 comicn1,2 display start com17 com18 com19 com20 com21 com22 com23 com24 com25 com26 com27 com28 com29 com30 com31 com32 com1, 17 com2, 18 com3, 19 com4, 20 com5, 21 com6, 22 com7, 23 com8, 24 com9, 25 com10, 26 com11, 27 com12, 28 com13, 29 com14, 30 com15, 31 com16, 32 comicn1,2 an example of common output executing display start from line address 30 h at 1/17 duty. an example of common output executing display start from line address 30 h at 1/33 duty.
a31 w33128 series preliminary (december, 2000, version 0.1) 21 amic technology, inc lcd drive output waveform (waveform b) the following is an example of how the common and segment drivers may be connected to a lcd panel. v5 v4 v3 v2 v1 vss com 1 m m v5 v4 v3 v2 v1 vss com 2 v5 v4 v3 v2 v1 vss seg 1 v5 v4 v3 v2 v1 vss seg 2 com 1 - s eg 1 v5 v4 v3 v2 v1 vss -v1 -v2 -v3 -v4 -v5 com 1 - s eg 2 v5 v4 v3 v2 v1 vss -v1 -v2 -v3 -v4 -v5 1/33 duty right/left alternate output common output pin 1/33 duty common output pin 1/17 duty common output pin 1 17 1 1 2 1 2 18 3 19 3 2 .... .... .... 16 32 32 32 com icn 1,2 1,2 1,2 1 17 1 1 2 18 2 17 3 19 3 2 .... 16 32 32 32 com icn 1,2 1,2 1,2
a31 w33128 series preliminary (december, 2000, version 0.1) 22 amic technology, inc examples of external bias resistor connection vs lcd drive waveform rd rd v 5 =v 2 v 1 =v 4 v 3 =v ss 1. 1/2 bias seg waveform com waveform m m m m r e1 v 5 v 2 v 4 v 1 v 3 v ss r e2 r e3 r e2 r e1 2. 1/2 to 1/3 bias seg waveform com waveform m m m m ) re (re re 2 1 3 + g = re 1 =re 3 1 0 g bias re 1 + re 2 = re 1 + re 2 + re 3 +re 2 +re 1 = 1 g + 2 r d v 5 v 4 =v 2 v 1 =v 3 v ss r d r d 3. 1/3 bias seg waveform com waveform m m m m r c1 v 5 v 4 v 2 v 3 v 1 v ss r c2 r c3 r c2 r c1 4. 1/3 to 1/4 bias seg waveform com waveform m m m m 1 0 b bias r c 1 = r c 1 + r c 2 + r c 3 +r c 2 +r c 1 = 1 3 b + r c 2 + r c3 =r c1 c1 c2 r r b = r b v 5 v 4 v 2 =v 3 v 1 r b r b 5. 1/4 bias seg waveform com waveform m m m m v ss r b r a 1 v 5 v 4 v 3 v 2 v 1 v ss r a 1 r a 2 r a 1 r a 1 6. 1/4 bias or more seg waveform com waveform m m m m a 0 bias r a 1 = r a 1 + r a 1 + r a 2 +r a 1 +r a 1 = 1 a + 4 1 2 ra ra a =
a31 w33128 series preliminary (december, 2000, version 0.1) 23 amic technology, inc absolute maximum ratings vss = 0.0v parameter symbol ratings unit supply voltage vdd - 0.4 to +6.0 v lcd drive voltage 1 v5 - 0.4 to +12 v lcd drive voltage 2 v1, v2, v3, v4 - 0.4 to v5 v input voltage v in - 0.4 to vdd+0.4 v output vo ltage v out - 0.4 to vdd+0.4 v operating temperature range topr - 30 to +85 c chip - 55 to +125 storage temperature range tab tstg - 55 to +100 c note 1 stresses above those listed under "absolute maximum ratings" may cause permanent damage to the devi ce. this is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note 2 exposure to absolute maximum rating conditions for e xtended periods may affect device reliability. note 3 when connecting a bias resistor externally, set the lcd power supply voltage so that the state is changed to v5 3 vdd. dc characteristics 1. electrical characteristics (unless otherwise specified: vdd = +5.0 0.5v, vss =0v, ta = - 30 to 85 c) parameter symbol conditions min. typ. max. unit note operating voltage vdd +2.4 - +5.5 v 1 v5 +2.7 - +11 v v1, v2 lcd drive voltage v3, v4 when using an external lcd power supply vss - v5 v 2 vdd=+2.4 to +4.5v 0.8xvdd - vdd high - l evel input voltage v ih vdd=+5.0 0.5v 0.8xvdd - vdd v 3 vdd=+2.4 to +4.5v vss - 0.2xvdd low - level input voltage v il vdd=+5.0 0.5v vss - 0.3xvdd v 3 i oh = - 0.5ma, vdd=+2.4 to+4.5v 0 .8xvdd - - v oh1 i oh = - i.0 ma 0.8xvdd - - v 4 i oh = - 50 m a, vdd=+2.4 to+4.5v 0.8xvdd - - high - level output voltage v oh2 i oh = - 120 m a 0.8xvdd - - v osco 5 i ol =0.5ma, vdd=+2.4 to +4.5v - - 0.2xvdd v ol1 i ol =1.0ma - - 0.2xvdd v 4 i ol =50 m a vdd=+2.4 to +4.5v - - 0.2xvdd low - level output voltage v ol2 i ol =120 m a - - 0.2xvdd v osco input leakage current i ileak vdd=+2.4 to +5.5v - 1.0 - 1.0 m a 5 output leakage current i oleak vdd=+2.4 to +5.5v - 3.0 - 3.0 m a 6 lcd driver on resistor r on ta=25 c, v5=+8.0v 1/5 bias - 3.0 5.0 k w 7 s tandby current i s - 0.05 5.0 m a 8 i ss1 external lcd power supply is used: during lc display v5=+8.0 v rf= 1 m w - 20.0 30.0 m a 9 during access: tcyc=200 khz vdd=+3.0 0.3 v - 150 450 operating current l ss2 during access: tcyc=200 khz - 300 m a 10 rf=1.0m w vdd=+3.0v 11 16 21 oscillating frequency f osc rf=1.0m w vdd=+5.0v 15 18 22 khz 11 wait time t r 10 - - m s 12
a31 w33128 series preliminary (december, 2000, version 0.1) 24 amic technology, inc 2. lcd power supply circuit electrical characteristics (unless otherwise specified: vdd = +2.4v to +5.5v, vss = 0v, ta = - 30 to 85 c) parameter symbol conditions min. typ. max. unit note operating voltage vdd +2.4 - +5.5 v 13 boosting output voltage v out triple boosting: up to vdd=3.6v double boosting: up to vdd=5.5v - - +11.0 v 1/4 bias +4.0 - +11.0 1/5 bias +4.5 - +11.0 lcd supply circuit operating voltage v5 1/6.7 bias +5.5 - +11.0 v 14 lcd driver operating voltage v lcd +2.7 - +11.0 v 15 built - in lcd circuit current consumption i ssl v out =+10.0 v double boosting vdd=+5.0 v v5=8.0v 1/5 bias osc. frequency : 18 khz - +90 +200 m a 16 external lcd power supply used: lcd drive current consumption l v5 v5=8.0v 1/5 bias - +30 +75 m a 17 d vref=+0.01%/ c +2.0 +2.2 +2.4 reference voltage v ref ta=25 c d vref= - 0.13%/ c +1.3 +1.5 +1.7 v 18 reference current i ref fin e adjustment data (1111) ta=25 c 1.5 2.5 4.0 m a 19 v1 1/4 * v5 - 0.1 1/4 * v5 1/4*v5+0.1 v2 2/4 * v5 - 0.1 2/4 * v5 2/4*v 5+0.1 v3 2/4 * v5 - 0.1 2/4 * v5 2/4*v 5+0.1 lcd drive bias voltage (1/4 bias) v4 v5=+4.0v to +11.0v 3/4 * v5 - 0.1 3/4 * v5 3/4*v 5+0.1 v1 1/5 * v5 - 0.1 1/5 * v5 1/5*v 5+0.1 v2 2/5 * v5 - 0.1 2/5 * v5 2/5*v 5+0.1 v3 3/5 * v5 - 0.1 3/5 * v5 3/5*v 5+0.1 lcd drive bias voltage (1/5 bias) v4 v5=+4.5v to +11.0v 4/5 * v5 - 0.1 4/5 * v5 4/5*v 5+0.1 v1 1/6.75 * v5 - 0.1 1/6.75 * v5 1/6.75*v 5+0.1 v2 2/6.75 * v5 - 0.1 2/6.75 * v5 2/6.75*v 5+0.1 v3 4.75/6.5 * v5 - 0.1 4.75/6.75 * v5 4.75/6.75* v5+0.1 lcd drive bias voltage (1/6.75 bias) v4 v5=+5.5v to +11.0v 5.75/6.75 * v5 - 0.1 5.75/6.75 * v5 5.75/6.75* v+0.1 v 20 3. references parameter symbol conditions min. t yp. max. unit note input pin capacity c in ta=25 c - 5 8 pf 3
a31 w33128 series preliminary (december, 2000, version 0.1) 25 amic technology, inc notes: 1. sharp variation in the supply voltage or input signal voltage due to strange noises may lead to a malfunction of the ic. supply stable supply voltage and input signal voltage. if you c hange the level of the supply voltage intentionally, a malfunction may occur. never change the level of the supply voltage. 2. when the external bias voltage is input, v5 3 v4, v3, v2, v1 3 vss, v5 3 vdd. there is no limitation for determining the voltage level of v1, v2, v3, and v4. 3. pins a0, cs , e, r/w, c68/80, p/s, osci, fnc1 and fnc2. pins d0 to d7 during display data write and command input. fully swing the levels v ih and v il of the input signal within the range of power supply voltage so th at the state is v ih =vdd, v il =vss. when the level of v ih and v il is the middle level of the supply voltage, the through current flowing through the input pin and the current consumption may be increased. 4. pins d0 to d7 during read. 5. pins a0 cs , e, r/w, c68/80, p/s, osci, fnc1 and fnc2. 6. pins d0 to d7 during write and high - impedance. 7. on resistance between lcd drive output pins (seg1 to seg128, com1 to 32, comicn1, and 2) and lcd drive bias voltage pins (vi, v2, v3, v4). using the external l cd power supply, measure the resistance at a 0.1 - v difference from the lcd drive output pin after applying 1/2 voltage of v5 to the lcd drive bias voltage pin. 8. power save state. when turning the input pin to "floating," the through current flows and will e ventually the power save effect may be reduced. 9. shows the current consumption during display including cr oscillation. it does not include the current consumed by the booster, lcd supply voltage adjustment circuit, voltage regulator, lcd bias resistor when using the external lcd power supply. the lcd drive output pin is no load. the current consumed by the lcd panel and wiring capacitor is not included. measure it without access from the mpu. the current consumed by the external lcd power supply and externa l bias resistor and other is not included. 10. the current consumption while the checkered pattern display data are being written from the mpu. the cr oscillation is measured while the cr oscillating circuit stops. the voltage level of the input signal is the v ih =vdd and v il =vss. when the input signal voltage is in the middle level, the current consumption may be increased. when the display data is written from the mpu during display, the state is changed to i ss1 +l ss2 . 11. shows the standard value at oscillating re sistor 1m w . determine appropriate oscillating frequency so as not to be in synchronization with the frame frequency and other frequency such as the fluorescent lamps. 12. shows the wait time from when the power voltage rises to 80 of the specified voltage to w hen the command input becomes available. 13. the operating voltage range of the booster. 14. shows the operating voltage range of the lc voltage adjustment circuit, voltage follower, and lcd bias resistor. the operating voltage range differs depending upon each bi as setting value. to adjust v5 with the lcd voltage adjustment circuit, it is necessary to set the voltage within the bias voltage. iv5i - iv out i 3 0.2v. 15. the operating voltage range of the lcd driver after the voltage follower functions. also, it shows t he voltage range of v1 to v5 supplied from the external lcd power supply circuit. 16. shows the value of the current consumed by the booster, lcd voltage adjustment circuit, voltage follower, lcd bias resistor, and lcd driver. it does not include the value irr eg=v5/(r1+r2+r3) of the current flowing through external resistors r1, r2, and r3. set the command fine adjustment data to 1000. outputs the checkered patterns from the lcd drive output pin. the pin is measured at "open." current consumption of the ic duri ng display is i ssl +l ss1 . 17. the built - in lcd power supply circuit stops when fnc1 and 2 are "h." current consumption only for the lcd driver. outputs the checkered patterns from the lcd drive output pin. the pin is measured at "open." current consumption of t he ic during display is iv5+ l ss1. when using the external power supply, stop the built - in power supply circuit which does not need to be operated with pins fnc1 and 2 to prevent the ic from being broken due to a shorting of the internal power supply. 18. the reference voltage differs depending upon the temperature coefficient selected with the corresponding command. 19. constant current which flows into the lcd voltage command fine adjustment circuit of the ic, for the fine adjustment data (1111). increasi ng the fine adjustment data by 1 bit, v5 increases by rb x i ref /15. 20. for the chips deliveries, chips are delivered after they satisfy their lcd drive bias voltages are 0.08v in the delivery testing at 25 c.
a31 w33128 series preliminary (december, 2000, version 0.1) 26 amic technology, inc timing characteristics 1. parallel interface 1.1 6 8 - series mpu read/write timing interface characteristics 68 - series mpu read/write timing characteristics (ta= - 30 to 85 c, vdd=+5v 10%) signal symbol designation conditions min. max. unit note t cyc6 system cycle time 500 - t ah6 address hold time 20 a0 cs , r/w t aw6 address setup time 20 t ds6 data setup time 80 - t dh6 data hold time 20 - t acc6 access time cl=15 pf 90 d0 to d7 t oh6 output disable time cl=15 pf 10 60 read 100 - e t ew enable pulse width write 80 - ns 68 - series mpu read/write timing characteristics (ta= - 30 to 85 c, vdd=+3v 10%) signal symbol designation conditions min. max. unit note t cyc6 system cycle time 1000 - t ah6 address hold time 4 0 - a0 cs , r/w t aw6 address setup time 40 - t ds6 data setup time 160 - t dh6 data hold time 40 - t acc6 access time cl=15 pf 180 d0 to d7 t oh6 output disable time cl=15 pf 10 120 read 200 - e t ew enable pulse width write 160 - ns note : rise/fall time of the input signal is 15 nsec or less. timing is specified at 20% or 80% of the signal waveform. t aw6 e d0 to d7 (write) r/w a0, cs db0 to db7 (read) t acc6 t ah6 t dh6 t ds6 t oh6 t ew t cyc6
a31 w33128 series preliminary (december, 2000, version 0.1) 27 amic technology, inc 1.2 80 - series mpu read/write timing characteristics 80 - series mpu read/write timing characteristics (ta= - 30 to 85 c, vdd=+5v 10%) signal symbol designation conditions min. max. unit note t ah8 address hold time 20 - a0 cs t aw8 address setup time 20 - t cyc8 system cycle time 500 - r/w, e t cc8 control pulse width 100 - t ds8 data setup time 8 0 t dh8 data hold time 20 - t acc8 e access time cl=15 pf 90 d0 to d7 t oh8 output disable time cl=15 pf 10 60 ns 80 - series mpu read/write timing characteristics when vdd=+3v (ta= - 30 to 85 c, vdd=+3v 10%) signal symbol designation conditions min. m ax. unit note t ah8 address hold time 40 - a0 cs t aw8 address setup time 40 - t cyc8 system cycle time 1000 - r/w, e t cc8 control pulse width 200 - t ds8 data setup time 160 - t dh8 data hold time 40 - t acc8 e access time cl=15 pf 180 d0 to d7 t oh8 output disable time cl=15 pf 10 120 ns note : rise/fall time of the input signal is 15 nsec or less. timing is specified at 20% or 80% of the signal waveform. t ah8 t aw8 t cyc8 t cc8 t ds8 t dh8 t oh8 t acc8 a0, cs r/w, e d0 to d7 (write) d0 to d7 (read)
a31 w33128 series preliminary (december, 2000, version 0.1) 28 amic technology, inc 2. serial interface serial interface t iming characteristics (ta= - 30 to 85 c, vdd=+5v 10%) signal symbol designation conditions min. max. unit note t css chip select setup time 50 cs t chs chip select hold time 400 t ass address setup time 120 a0, r/w t ahs address hold time 200 t dss data setup time 120 d0 (sdi) t dhs data hold time 50 t cycs clock cycle time 500 t clls clock l time 200 d1 (sclk) t clhs clock h time 200 t dds data delay time cl=15 pf 90 d2 (sdo) t ohs data dis able time cl=15 pf 10 60 ns 1 serial interface timing characteristics (ta= - 30 to 85 c, vdd=+3v 10%) signal symbol designation conditions min. max. unit note t css chip select setup time 100 cs t chs chip select hold time 800 t ass address setup time 240 a0, r/w t ahs address hold time 400 t dss data setup time 240 d0 (sdi) t dhs data hold time 100 t cycs clock cycle time 1000 t clls clock l time 400 d1 (sclk) t clhs clock h time 400 t dds data delay time cl=15 pf 180 d2 (sdo) t ohs data disable time cl=15 pf 10 120 ns 1 note : 1. d2(dso) is high - impedance at the rising edge of the cs . 2. rise/fall time of the signal is 15 nsec. or less 3. timing is specified at 20% or 80% of the signal waveform. serial interface read/write timing characteristics d1 (sclk) r/w cs t chs t ahs t ohs t cs t ass t clls t cycs t clhs t dds t dss t dhs a0 d0 (sdi) d2 (sdo)
a31 w33128 series preliminary (december, 2000, version 0.1) 29 amic technology, inc examples of applications of lcd power supply reference c : 1.0 m f c1 : 0.47 m f c2 : 0.1 m f c3 : 0.01 m f capacitor c3 connected to v3 pin is recommended 0.01 m f . when using a built-in lcd power supply circuit (triple boosting) vss c c c vss c1+ c1- c2+ c2- v out rf osc osc2 vdd vdd c r1 r2 r3 vss vss v1 v2 v3 v4 vss fnc1 fnc2 v cnt v5 . when using an external regulator . when using an external boosting power supply vss vss c1+ c1- c2+ c2- v out rf osc osc2 vdd vdd c r1 r2 r3 vss vss v1 v2 v3 v4 vss fnc1 fnc2 v cnt v5 external boosting power supply c vdd vss vss c1+ c1- c2+ c2- v out rf osc osc2 vdd vdd c vss vss v1 v2 v3 v4 fnc1 fnc2 v cnt v5 external regulator c vdd . when using an external lcd power supply vss vss c1+ c1- c2+ c2- v out rf osc osc2 vdd vdd vss v1 v2 v3 v4 fnc1 fnc2 v cnt v5 v lc vss vss vdd c c c c c c c c c c c c
a31 w33128 series preliminary (december, 2000, version 0.1) 30 amic technology, inc booster capa citor connection reference c : 1.0 m f c1 : 0.47 m f tripler doubler vss c1 c1 c vs c1- c1+ c2- c2+ v out vss c1 c1 open vs c1- c1+ c2- c2+ v out
a31 w33128 series preliminary (december, 2000, version 0.1) 31 amic technology, inc examples of connection to lcd panels 2. 1/33 duty 17 x 256 panel 1. 1/17 duty 17 x 128 panel . com1 to 16 are used: lcd17 x 128 1........128 icon icon .... 1 16 se a31w33128 com icn2 com icn1 com 1 to 16 . com17 to 32 are used: lcd17 x 128 1........128 icon icon se a31w33128 com icn2 com icn1 .... 1 16 com 17 to 32 lcd17 x 256 1........128 icon icon se a31w33128 com icn2 com icn1 .... 17 32 com 17 to 32 com 1 to 16 .... 1 16 129........256
a31 w33128 series preliminary (december, 2000, version 0.1) 32 amic technology, inc 3. 1/33 duty 33 x 128 panel 3.1 normal common output 3.2 common right/left alternate output output in a numerical order of common pin nos. even-numbered common line uneven-numbered common line lcd 33 x 128 1........128 icon icon se a31w33128 com icn2 com icn1 .... 1 16 .... 17 32 com 1 to 16 com 17 to 32 lcd 33 x 128 1........128 icon icon se a31w33128 com icn2 com icn1 .... 1 3 29 31 com 1 to 16 com 17 to 32 .... 2 4 30 32 examples of connection to lcd panels (continued)
a31 w33128 series preliminary (december, 2000, version 0.1) 33 amic technology, inc ordering information part no. package a31w33128c cog A31W33128T tcp

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